1. Field of the Invention
The present invention relates to a battery state monitoring circuit provided with a charge control transistor gate connection terminal, a discharge control transistor gate connection terminal, an overcurrent voltage detection terminal, and a microcomputer control terminal.
2. Description of the Related Art
In general, as shown in FIG. 2, a battery state monitoring circuit 22A is provided with respective battery voltage monitor terminals 5A to 9A, a charge control transistor gate connection terminal 10A (hereinafter sometimes referred to as a COP terminal), a discharge control transistor gate connection terminal 11A (hereinafter sometimes referred to as a DOP terminal), an overcurrent voltage detection terminal 12A (hereinafter sometimes referred to as a VMP terminal), and a microcomputer control terminal (hereinafter sometimes referred to as a CTL terminal) 13A. A rechargeable battery device is comprised of a charge control transistor 14A, a discharge control transistor 16A, a VMP terminal pull-up resistor 18A, and secondary batteries 1A to 4A. A microcomputer up 21A is connected to the CTL terminal 13A, and a load 19A and a charger 20A are connected between external terminals EB+ and EB− of the battery device.
The VMP terminal 12A is pulled up to VDD by the pull-up resistor 18A in a normal state. The VMP terminal 12A monitors a voltage between VDD and the VMP terminal, detects that the voltage is lowered from VDD by a certain voltage, and causes the DOP terminal 11A to output “H”. That is, VMP=“L” leads to DOP=“H”, and the discharge control transistor 16A is turned OFF.
The CTL terminal 13A is a terminal for carrying out communication between the battery state monitoring circuit 22A and the microcomputer 21A. In FIG. 2, showing the conventional circuit, when a charge inhibiting signal (here, an overcharge inhibiting signal is assumed to be “H”) is input to the CTL terminal 13A, the COP terminal 10A is made to output “H”. That is, CTL=“H” leads to COP=“H”, and the charge control transistor 14A is turned OFF. Here, arrows shown in FIG. 2 indicate the flow of signals.
FIG. 4 is a timing chart showing the relation between signals at the CTL, VMP and COP terminals of the conventional battery state monitoring circuit and the rechargeable battery device using the same. In accordance with FIG. 4, when the charge inhibiting signal is input from the microcomputer 21A to the CTL terminal 13A, the COP terminal 10A outputs “H” to turn OFF the charge control transistor 14A to stop charging of the secondary batteries 1A-4A. When the VMP terminal voltage reaches a detection voltage by a signal of overcurrent or the like, the DOP terminal outputs “H” to turn OFF the discharge control transistor 16A.
That is, when CTL=“H”, it is determined COP=“H” irrespective of the signal of the VMP terminal 12A.
In the conventional battery device, when the charge inhibiting signal is inputted to the CTL terminal 13A from the microcomputer 21A, both the charge control transistor 14A and the discharge control transistor 16A are turned OFF, and there has been a problem in that even if a load is connected between the terminals EB+ and EB−, it is locked in a state where a battery voltage can not be supplied.
In FIG. 2, when the charge inhibiting signal is inputted from the microcomputer 21A to the CTL terminal 13A, the COP terminal 10A outputs “H”, and the charge control transistor 14A is turned OFF. At this time, if the load is connected between the terminals EB+ and EB−, since a current flows through a parasitic diode 15A of the charge control transistor 14A, a voltage drop of a junction voltage (VF) of the parasitic diode 15A is generated between the VDD and the EB+. Here, since the VMP terminal 12A monitors the voltage between the VDD and the VMP terminal, overcurrent detection is caused by the voltage drop, the DOP terminal outputs “H”, and the discharge control transistor M2 is turned OFF.